1. Field of the Invention
The present invention relates to multiplex conversion equipment in a digital synchronization network, more particularly a time slot assignment circuit (hereinafter also referred to as a TSA circuit) for performing channel setting in multiplex conversion equipment.
In digital synchronization networks, it has become possible to perform channel setting in a time domain (interchanging positions of channels in a time slot train) by assignment of time slots on a digital multiplex level (for example STS-12 and STS-48). As a result, it has become possible to realize multiplex conversion equipment. The present invention relates to a TSA circuit, more particularly a TSA circuit which can easily realize a rise in transmission rates and enlargement of capacity and which has a high efficiency and a high degree of freedom in the combinations of the channel settings.
2. Description of the Related Art
As will be explained in detail later by using the drawings, the TSA circuit of the related art had two combining circuits and registers for each channel (CH) and realized the TSA of all channels (CH) by performing TSA (channel setting) for each block (CH) and serially connecting them.
In addition, since the transmission capacity was relatively low speed data signals of, for example, the STS-48 (2.4 Gb/s) level compared with the STS-192 (10 Gb/s) level, a TSA circuit could be realized by a multistage connection of simple circuits (shift registers) configured by the channel (CH) units.
In a rise of transmission rates and increase of capacity expected in the future, a transmission method of high efficiency offering a high degree of freedom in the combination of channel settings has been sought. However, the increase of capacity has been accompanied by not only an increase in the circuit scale, but also the number of channel numbers, therefore the number of combinations of channel settings has increased. If trying to realize this by the circuit of the related art, the number of nets would become enormous, there would be insufficient timing margins, the layout on the chip would become difficult, and there would be other possible obstacles to development.
There has been dazzling progress made in the integration technology for LSIs in recent years, but there are still various limitations. These limitations have become obstacles to realization of a TSA function in circuit design. More specifically, in the TSA (channel setting) of the STS-48 (2.4 Gb/s) level of the related art, that is, the STS-48-TSA, it is sufficient to realize 2,304 types of combinations of channels, but in the STS-192-TSA planned by the present invention, up to 36,864 types of combinations of channels must be realized, therefore a circuit 16 times the size in the case of the STS-48-TSA becomes necessary.
In addition to this increase of circuit size, since the transmission rate (bit rate of signals to be processed) becomes high, the power consumption naturally becomes larger.
Accordingly, there is a problem of disadvantageous circuit size, power consumption, timing margin, and degree of integration to a chip (number of nets) if a TSA circuit structure comprising only logics of the related art is applied as it is to the TSA circuit of the STS-192 level.